Analysis of DDR3 SDRAM Standard Technology

Implementation of the Complete Predictor for DDR3 SDRAM

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They can suppress the latencies when accessing cache or main memory. In our previous work we proposed predictors that not only close the opened DRAM row but also predict the next row to be opened, hence the name ‘Complete Predictor’. It requires less tha...

New SEE Test Results for 4 Gbit DDR3 SDRAM

New generation 4 Gbit DDR3 SDRAMs from Samsung and Elpida have been tested for hard errors and device SEFIs under heavy ions.

Dual DIMM DDR2 and DDR3 SDRAM Interface Design Guidelines

This application note describes guidelines for implementing dual unbuffered DIMM DDR2 and DDR3 SDRAM interfaces. This application note discusses the impact on signal integrity of the data signal with the following conditions in a dual-DIMM configuration: ■ Populating just one slot versus populating both slots ■ Populating slot 1 versus slot 2 when only one DIMM is used ■ On-die termination (ODT...

Challenges in implementing DDR3 memory interface on PCB systems: a methodology for interfacing DDR3 SDRAM DIMM to an FPGA

Sdram Space Radiation Effects Measurements and Analysis

In recent years, memory technology has been advancing quickly. This paper presents the comprehensive radiation effects examination of two high density (64Mb and 128Mb) 0.35 μm CMOS Synchronous Dynamic Random Access Memories (SDRAMs). This study uses the major components of the natural near earth environment to determine the applicability of these parts to space missions. Protons have been used ...